1. Field of the Invention
This invention is directed to computing apparatus circuitry, in general, and to a minicomputer circuit with relatively high speed multiplication in floating point numbers, in particular.
2. Prior Art
There are many known computing systems available in the art. Many of these computing systems utilize multiple bit information trains made up of multiple words to store or represent a number. In many cases, it is desirable (or necessary) to multiply two or more of these numbers. In many cases, the information trains representing the numbers may contain a number of trailing zeros. This is most common in floating point arithmetic when an integer is represented in the floating point number format. If a step-wise multiplication operation of known configuration is utilized, a long string of trailing zeros in the respective words will require an extended number of system operations wherein the multiplication operation is extremely slow and, consequently, limitative of the system operating speed. In the past, some techniques have been utilized to speed up this multiplication process; however, many of the known techniques require extensive adjustments in the computing system and wholesale revisions to the existing circuitry. That is, the speed of the multiplication operation is provided at the expense of an increase in the size of the circuit apparatus and complexity of the existing circuitry. However, all of the known techniques are either cumbersome, expensive or otherwise undesirable and inconvenient for use in existing computing circuitry.